`timescale 100ns / 100ps

                       
module tb_staining
    (   output logic                    clk
        );
//*********************** КОНСТАНТЫ ****************************************************************

//*********************** СОЗДАНИЕ И ОПИСАНИЕ ПЕРЕМЕННЫХ *******************************************
    logic               reset_n;
    
    logic               wre_i, wre_o;
    logic [15:0]        data_i;
    logic [7:0]         data_o;
    logic [31:0]        addr_i, addr_o;    
//********************** БЛОК НЕПРЕРЫВНЫХ НАЗНАЧЕНИЙ ASSIGN ****************************************


//********************** ОПИСАНИЕ ПОДКЛЮЧАЕМЫХ БЛОКОВ ***********************************************

mod_staining
    #(  .width_p        (8),
        .height_p       (128)
    )
mod_staining_inst
    (   .reset_n    (reset_n),
        .clk        (clk),

        .wre_i      (wre_i),
        .data_i     (data_i),
        .addr_i     (addr_i),
        
        .wre_o      (wre_o),
        .data_o     (data_o),
        .addr_o     (addr_o)
    );
  
// ********************* БЛОКИ ИНИЦИАЛИЗАЦИИ *******************************************************
    initial begin
        reset_n = 0;
    #25  reset_n = 1;
    end
    
    initial begin        // CLK
        clk = 0;
        forever #5ns clk = ~clk;
    end
    
    initial begin
        repeat (5) begin
            addr_i  = 0;
            data_i  = 0;
            wre_i   = 0;
            #100;
            repeat (1032) begin
                data_i  = addr_i*0.01 + 2000;
                wre_i   = 1;
                @(posedge clk);
                addr_i  = addr_i + 1;
            end
        end
    end    
endmodule